EntryUpdated 2026/08/08

Why Is the Chip Supply Chain Stuck in So Few Places?

Because every layer has its own bottleneck, and the bottlenecks sit in different countries. And because diversifying design does not offset concentration in manufacturing — they are risks at different layers.

The bottlenecks sit in different countries, so no one can undo them alone

Chip design and EDA softwareUnited States
Design tools are the entrance to the whole chain: without EDA there is no manufacturable layout. That also makes it one of the most effective points to apply controls.
Advanced lithographyASML, Netherlands
EUV lithography has a single supplier. This is the sharpest concentration in the chain, and the reason the Netherlands is drawn into US–China control disputes.
Materials and certain critical equipmentJapan
Photoresists, speciality chemicals, and several process tools. Their share of cost is often tiny and their absence halts the line — this is where single points of failure like to hide.
Leading-edge process and foundryTaiwan
Separating foundry from design lowered the barrier to entry but concentrated manufacturing risk into a handful of sites. TSMC is expanding 3nm-related capacity in Taiwan, the United States, and Japan, ramping through 2027–2028.
MemoryMainly South Korea
More suppliers than the layers above, yet high-bandwidth memory is just as tight — training throughput depends on memory bandwidth keeping pace.
Packaging, test, and final assemblyChina and Southeast Asia
The most dispersed and most relocatable layer — though advanced packaging is climbing toward the leading edge and turning part of it into a new bottleneck.

Highly concentrated — few suppliers, not substitutable near-termPartly concentrated — more suppliers, capacity still tightRelatively dispersed — relocatable, but climbing toward the edge

“The supply chain is concentrated” says little on its own: concentrated at which layer, in whose hands, and how substitutable are three separate questions. Laid out, two things appear: the top four layers each have only a few suppliers, and those suppliers sit in different countries; and diversifying design does not offset concentration in manufacturing — they are risks at different layers.
What a newcomer faces is not a technology gap but a time gap. Subsidies build fabs; they do not buy yield. A building is a capital problem, yield is an experience problem.Source: Impactful Creative, compiled from the division of labour described in our chip-war analysis and the glossary entries on leading-edge process, foundry, and single points of failure

What layers does a chip pass through?

For three decades semiconductors were globalisation’s most refined division of labour: the United States in design and EDA software, Japan in materials and certain critical equipment, ASML in the Netherlands in advanced lithography, Taiwan in leading-edge process and foundry, South Korea in memory, and China in final assembly and as an enormous market.

The system rested on cost, efficiency, and specialisation, and it is what drove down the price of smartphones, cloud computing, and consumer electronics.

The key point: this is not one production line that can be relocated wholesale, but six layers that each evolved separately over decades. No layer is closed by building a single plant.

Why does each layer come down to a handful of firms?

Because the barriers compound. Equipment only sells once someone will risk a production line to qualify it; a process only matures after enough real production to fix yield; materials often take years to certify.

What a newcomer faces is not a technology gap but a time gap — and the leaders do not pause to wait.

Which is why subsidies can build a fab but cannot buy yield. A building is a capital problem; yield is an experience problem.

Where do single points of failure usually hide?

Not in the most expensive or most visible step. A single point of failure is more often a speciality chemical, one packaging plant, or a particular inspection tool — a tiny share of cost whose absence halts the line.

They are hard to find because they sit at the third or fourth tier, while most firms can see only the first. Knowing your suppliers is not knowing your suppliers’ suppliers.

It also explains why “we have two suppliers” is not necessarily redundancy: both may buy the same material from the same source.

Do overseas fabs solve the concentration problem?

They reduce the risk of any single site, but they do not make the layer less concentrated. A new fab still needs the same equipment, the same materials, and the same experienced engineers — the location changes, the upstream bottlenecks do not.

And the timescale is years. TSMC is expanding 3nm-related capacity in Taiwan, the United States, and Japan, ramping through 2027–2028 — years after the announcements.

Two things need separating in any resilience discussion: geographic dispersion addresses the risk that one place goes down; industrial concentration addresses the risk that only a few firms in the world can do it at all. The first is achievable; the second is not, in the near term.

How reliable is the “silicon shield” argument?

The silicon shield argument holds that Taiwan’s irreplaceable position in the chip supply chain is itself a deterrent: destroying that capacity would damage the global economy, so everyone has an incentive to preserve the status quo.

The dispute is that this assumes rational calculation outweighs political motive. History is not short of costly conflicts, and “expensive” has never implied “will not happen.”

Overseas expansion is read both ways — as diversifying risk, and as diluting the shield. Both readings hold, because they answer different questions: one asks whether capacity is safe, the other asks whether Taiwan’s bargaining position has changed.

Terms used here

Advanced Node — The leading generation of chip manufacturing, dependent on equipment — extreme ultraviolet lithography above all — available from a very small number of suppliers. Advanced nodes are the primary target of export controls because they combine high technical barriers, extreme geographic concentration, and clear military relevance. Where the control line is drawn between nodes shapes the industry more than the existence of controls does.
Foundry — The model in which a manufacturer fabricates chips designed by others and sells no products of its own. Separating fabrication from design lowered entry barriers for designers, but concentrated the industry's manufacturing risk into a handful of sites. In resilience terms, diversity at the design layer does not offset concentration at the fabrication layer; they are distinct risks.
Single Point of Failure — A node whose failure halts the entire chain. It is rarely the most expensive or most visible link — more often a specialty chemical, a sole packaging facility, or a particular test instrument accounting for a trivial share of cost. Mapping these is hard because they typically sit at tier three or four, while most companies have visibility only to tier one.
Silicon Shield — The proposition that Taiwan's irreplaceable position in global chip supply is itself a deterrent: disrupting that capacity would damage every major economy, so all parties have an interest in the status quo. The argument is contested because it assumes economic calculation outweighs political motivation — and overseas fab expansion is read simultaneously as risk diversification and as dilution of the shield.